1. Technical Field
The present invention relates to an interprocessor communication device in a digital system having at least two processors, and more particularly to an interprocessor communication device with a message passing network allowing rapid transfer of messages between a plurality of processors.
2. Related Art
For high performance and real-time data processing, two or more processor modules can be loaded into a digital system such as a digital data transmission system, a digital switching system, and a network server for processing data from a plurality of clients. Each processor module includes at least one microprocessor.
In order to rapidly process a large amount of digital data, the digital system should be provided with an interprocessor communication (IPC) device for transferring messages between a plurality of processor modules processing elements after their own functions. As is known, interprocessor communication is generally implemented through a shared memory like a dual port random access memory (RAM), but this allows no concurrent access of two processors to data, thus lowering interprocessor communication efficiency.
Exemplars of recent efforts in the art include U.S. Pat. No. 5,787,300 for a Method and Apparatus for Interprocess Communications in a Database Environment issued to Wijaya, U.S. Pat. No. 5,778,429 for a Parallel Processor System Including a Cache Memory Subsystem That Has Independently Addressable Local and Remote Data Areas issued to Sukegawa et al., U.S. Pat. No. 5,745,779 for a Network Subsystem for Parallel Processor System and Network System for Parallel Processor System issued to Katori, U.S. Pat. No. 5,745,778 for an Apparatus and Method for Improved Cpu Affinity in a Multiprocessor System issued to Alfieri, U.S. Pat. No. 4,507,728 for a Data Processing System for Parallel Processing of Different Instructions issued to Sakamoto et al., U.S. Pat. No. 5,742,766 for a Parallel Computing System for Synchronizing Processors by Using Partial Switch Circuits for Broadcasting Messages after Receiving Synchronization Signals and Judging Synchronization Thereof issued to Takeuchi et al., U.S. Pat. No. 5,630,156 for a Process for Parallel Operation of Several Computation Units, Especially in Image Processing, and Corresponding Architecture issued to Privat et al., U.S. Pat. No. 5,287,532 for a Processor Elements Having Multi-byte Structure Shift Register for Shifting Data Either Byte Wise or Bit Wise with Single-bit Output Formed at Bit Positions Thereof Spaced by One Byte issued to Hunt, and U.S. Pat. No. 5,249,301 for a Processing Communication System Having a Plurality of Memories and Processors Couples Through at Least One Feedback Shift Register Provided from Ring Configured Input Stations issued to Keryvel et al.
While these recent efforts provide advantages, I note that they fail to adequately provide an enhanced, efficient interprocessor communication device with a message passing network allowing rapid transfer of messages between a plurality of processors.